bai 1

library ieee;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

entity add4 is

port

(

a: in std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0);

cin : in std_logic;

cout: out std_logic;

sum: out std_logic_vector(3 downto 0)

);

end add4;

architecture structure of add4 is

------cai dat componet----------

component full_add is

port (

a: in std_logic;

b: in std_logic;

cin : in std_logic;

cout: out std_logic;

sum: out std_logic

);

end component;

------- khai lbao tin hieu--

signal c1: std_logic;

signal c2: std_logic;

signal c3: std_logic;

---------begin---------------

begin

u0: component full_add

port map(a(0),b(0),cin,c1,sum(0));

u1: component full_add

port map(a(1),b(1),c1,c2,sum(1));

u2: component full_add

port map(a(2),b(2),c2,c3,sum(2));

u3: component full_add

port map(a(3),b(3),c3,cout,sum(3));

end structure;

------------

library ieee;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

entity full_add is

port (

a: in std_logic;

b: in std_logic;

cin : in std_logic;

cout: out std_logic;

sum: out std_logic

);

end full_add;

architecture dataflow of full_add is

begin

sum <= a xor b xor cin;

cout <= (a and b) or (cin and (a xor b));

end dataflow;

============

bai 2

library ieee;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

entity ic74138 is

port (

abc: in std_logic_vector(2 downto 0);

y: out std_logic_vector(7 downto 0);

enable: in std_logic

);

end ic74138;

architecture behavioral of ic74138 is

begin

process (abc,enable)

begin

if enable = '0' then

   y<=(others =>'1');

   else

        case abc is

            when "000"     => y<=x"7f";

            when "001"     => y<=x"bf";

            when "010"     => y<=x"df";

            when "011"     => y<=x"ef";

            when "100"     => y<=x"f7";

            when "101"     => y<=x"fb";

            when "110"     => y<=x"fd";

            when others => y<=x"fe";

        end case;

end if;

end process;

end behavioral;

=================

bai 3

library ieee;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

entity mux is

generic (n: natural :=4);

port(

x0: in std_logic_vector(n-1 downto 0);

x1: in std_logic_vector(n-1 downto 0);

x2: in std_logic_vector(n-1 downto 0);

x3: in std_logic_vector(n-1 downto 0);

y: out std_logic_vector(n-1 downto 0);

sel: in std_logic_vector(1 downto 0);

enable: in std_logic

);

end mux;

architecture behavioral of mux is

begin

process (enable,sel,x0,x1,x2,x3)

begin

if enable = '0' then

  y<=(others =>'0');

   else

    case sel is

       when "00"  => y<=x0;

       when "01"  => y<=x1;

       when "10"  => y<=x2;

       when others=> y<=x3;

    end case;

end if;

end process;

end behavioral;

=============

bai 4

library ieee;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_1164.all;

entity demux is

generic (n: natural :=4);

port(

x: in std_logic_vector(n-1 downto 0);

y0: out std_logic_vector(n-1 downto 0);

y1: out std_logic_vector(n-1 downto 0);

y2: out std_logic_vector(n-1 downto 0);

y3: out std_logic_vector(n-1 downto 0);

sel: in std_logic_vector(1 downto 0);

enable: in std_logic

);

end demux;

architecture behavioral of demux is

begin

process (enable,sel,x)

begin

if enable = '0' then

   y0<=(others =>'0');

   y1<=(others =>'0');

   y2<=(others =>'0');

   y3<=(others =>'0');

   else

    case sel is

       when "00"  => y0<=x;

       when "01"  => y1<=x;

       when "10"  => y2<=x;

       when others=> y3<=x;

    end case;

end if;

end process;

end behavioral;

=============

bai 5

library ieee;

use ieee.std_logic_arith.all;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity addsub is

port(

a: in std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0);

cin: in std_logic;

sub: in std_logic;

cout: out std_logic;

product: out std_logic_vector(3 downto 0)

);

end addsub;

architecture dataflow of addsub is

signal a1: std_logic_vector(4 downto 0);

signal b1: std_logic_vector(4 downto 0);

signal product1: std_logic_vector(4 downto 0);

signal notb1: std_logic_vector(4 downto 0);

begin

a1<='0'& a;

b1<='0'& b;

notb1<= not b1;

product<= product1(3 downto 0);

process (sub,a1,b1,notb1,cin,product1)

begin

if sub ='1' then

    product1<= a1 + notb1 +1;

    else

    product1<= a1 + b1 +cin;

    cout<=product1(4);

end if;

end process;

end dataflow;

=============

bai 6

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity cmp is

port

(

a: in std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0);

abin: in std_logic_vector(2 downto 0);

abo: out std_logic_vector(2 downto 0)

);

end cmp;

architecture behavioral of cmp is

constant lon: std_logic_vector(2 downto 0) :="100";

constant be : std_logic_vector(2 downto 0) :="010";

constant bang: std_logic_vector(2 downto 0) :="001";

begin

process(a,b,abin)

begin

if a(3)> b(3)  then

       abo <=lon;

    elsif a(3)<b(3) then

        abo<=be;

    elsif a(2)>b(2) then

        abo<=lon;

    elsif a(2)<b(2) then

        abo<=be;

     elsif a(1)>b(1) then

        abo<=lon;

    elsif a(1)<b(1) then

        abo<=be;

    elsif a(0)>b(0) then

        abo<=lon;

    elsif a(0)<b(0) then

        abo<=be;

    elsif abin = lon then

        abo<=lon;

    elsif abin = be then

        abo<=be;

    elsif abin = bang then

        abo<=bang;

end if;       

 end process;

end behavioral;

============

bai 7

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity ic7447 is

port (

nbcd: in std_logic_vector(3 downto 0);

q: out std_logic_vector(6 downto 0);

lt: in std_logic

);

end ic7447;

architecture behavioral of ic7447 is

begin

process(lt,nbcd)

begin

if lt ='0' then

  q<=(others =>'0');

 else

 case nbcd is

  when "0000" => q<="0000001";

  when "0001" => q<="1001111" ;

    when "0010"    => q<="0010010";

    when "0011"    => q<="0000110" ;

    when "0100"    => q<="1001100" ;

    when "0101"    => q<="0100100" ;

    when "0110"    => q<="1100000" ;

    when "0111"    => q<="0001111" ;

    when "1000"    => q<="0000000" ;

    when "1001"    => q<="0001100" ;

    when others => q<=    "1111111";

    end case;

 end if; 

 end process;

end behavioral;

================

bai 8

dff :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity dff is

port(

d: in std_logic;

clk: in std_logic;

reset: in std_logic;

set: in std_logic;

q: inout std_logic;

notq: inout std_logic

);

end dff;

architecture behavioral of dff is

begin

notq<=not q;

process(d,clk,reset,set,q,notq)

begin

 if reset ='1' then

   q<='0';

   elsif set ='1' then

    q<='1';

   elsif clk ='1' and clk'event then

        q<=d;

end if;

end process;

end behavioral;

----------------

tff:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity tff is

port(

t: in std_logic;

clk: in std_logic;

reset: in std_logic;

set: in std_logic;

q: inout std_logic;

notq: inout std_logic

);

end tff;

architecture behavioral of tff is

begin

notq<=not q;

process(t,clk,reset,set,q,notq)

begin

 if reset ='1' then

    q<='0';

   elsif set ='1' then

    q<='1';

   if clk ='1' and clk'event then

        q<=t xor q;

end if;

end process;

end behavioral;

================

bai 8

------jkff------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity jkff is

port(

j: in std_logic;

k: in std_logic;

clk: in std_logic;

reset: in std_logic;

set: in std_logic;

q: inout std_logic;

notq: inout std_logic

);

end jkff;

architecture behavioral of jkff is

begin

notq<=not q;

process(j,k,clk,reset,set,q,notq)

begin

if reset ='1' then

 q<='0';

 elsif set ='1' then

  q<='1';

  elsif clk ='1' and clk'event then

    q<=(j and notq) or ((not k) and q);

    end if;

    end process;

end behavioral;

---------rsff---------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity rsff is

port(

r: in std_logic;

s: in std_logic;

clk: in std_logic;

reset: in std_logic;

set: in std_logic;

q: inout std_logic;

notq: inout std_logic

);

end rsff;

architecture behavioral of rsff is

signal cam: std_logic;

signal kxd: std_logic;

begin

notq<=not q;

cam<= r and s;

process(r,s,cam,clk,reset,set,q,notq)

begin

 if reset ='1' then

   q<='0';

   elsif set ='1' then

    q<='1';

   elsif clk ='1' and clk'event then

     if cam ='0' then

        q<=s or ((not r) and q);

      else

      q<=kxd;

     end if;

end if;

end process;

end behavioral;

==============

bai 10

----------mux_n----------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity mux_n is

generic (n: natural :=32);

port (

        a: in std_logic_vector(n-1 downto 0);

        b: in std_logic_vector(n-1 downto 0);

        sa: in std_logic;

        m:out std_logic_vector(n-1 downto 0)

);

end mux_n;

architecture behavioral of mux_n is

begin

mux:process(a,b,sa)

begin

case sa is

     when '0' =>     m<=a;

     when others =>  m<=b;

     end case;

 end process mux;

end behavioral;

------------reg_n---------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity reg_n is

generic (n: natural :=32);

port(

        d: in std_logic_vector(n-1 downto 0);

        q: out std_logic_vector(n-1 downto 0);

        clk: in std_logic;

        reset: in std_logic

);

end reg_n;

architecture behavioral of reg_n is

begin

process(clk,reset,d)

begin

if reset ='1' then

    q<=(others =>'0');

 elsif clk = '1' and clk'event then

    q<= d;

  end if;

end process;

end behavioral;

-------------reg_shift------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity reg_shift is

generic (n: natural := 32);

port(

        din: in std_logic_vector(n-1 downto 0);

        q: inout std_logic_vector(n-1 downto 0);

        sa: in std_logic_vector(4 downto 0);

        we: in std_logic;

        clk: in std_logic;

        reset: in std_logic

);

end reg_shift;

architecture structure of reg_shift is

--------- cai dat component ----------

component shift is

generic (n:natural :=32);

port (

        sh_in: in std_logic_vector(n-1 downto 0);

        sa: in std_logic_vector(4 downto 0);

        sh_out: out std_logic_vector(n-1 downto 0)

);

end component;

component mux_n is

generic (n: natural :=32);

port (

        a: in std_logic_vector(n-1 downto 0);

        b: in std_logic_vector(n-1 downto 0);

        sa: in std_logic;

        m:out std_logic_vector(n-1 downto 0)

);

end component;

component reg_n is

generic (n: natural :=32);

port(

        d: in std_logic_vector(n-1 downto 0);

        q: out std_logic_vector(n-1 downto 0);

        clk: in std_logic;

        reset: in std_logic

);

end component;

----- khai bao tin hieu---------

signal sho: std_logic_vector(n-1 downto 0);

signal m_out:std_logic_vector(n-1 downto 0);

------begin -------------------

begin

        u0: component shift

        generic map(n)

        port map(q,sa,sho);

        u1: component mux_n

        generic map(n)

        port map(sho,din,we,m_out);

        u2: component reg_n

        generic map(n)

        port map(m_out,q,clk,reset);

end structure;

--------------shift----------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

use ieee.numeric_bit.all;

entity shift is

generic (n: natural :=32);

port (

        sh_in: in std_logic_vector(n-1 downto 0);

        sa: in std_logic_vector(4 downto 0);

        sh_out: out std_logic_vector(n-1 downto 0)

);

end shift;

architecture dataflow of shift is

signal shi: bit_vector(n-1 downto 0);

signal sho: bit_vector(n-1 downto 0);

signal nsa: integer;

begin

shi<= to_bitvector(sh_in);

nsa<= conv_integer('0' & sa);

sho<= shi srl nsa;

sh_out<= to_stdlogicvector(sho);

end dataflow;